In a conventional complementary metal oxide semiconductor (CMOS) integrated circuit fabrication, and assuming an N type semiconductor substrate, the first stage includes the photoresist masking and etching of the silicon oxide layer on the substrate to form openings therein for the P- diffusion into the N substrate. The second masking and etching of the silicon oxide layer is to form openings for the P+ diffusion regions forming the drain and source for the P channel gate devices. The third masking and etching step in the silicon oxide layer is utilized to form the openings for the source and drain N+ diffusions for the N channel gate devices in the P- diffused regions. A fourth masking and etching step is used to form the openings through the silicon oxide at the gate regions of the P channel and the N channel devices, the thin gate oxide film thereafter being thermally grown. The fifth masking and etching step is provided to form the contact openings through the silicon oxide layer to the various P+ and N+ source, drain and substrate regions. The sixth masking step is used to form the metal interconnections between the various contact openings and to define the metal gate electrodes over the thin gate oxide film in the channel regions of the gate devices. In this conventional CMOS fabrication, the gate regions for the various gate devices are defined after the P+ and N+ diffusion, i.e., with the fourth masking step. It is necessary to make oversized gate openings to be sure that the gate regions overlap the P+ source and drain regions and the N+ source and drain regions, taking into consideration the normal amount of mask misalignment in the P+ and N+ masking steps. A tolerance figure of 0.1 mil is typical and the gate areas must be large enough to take into consideration this normal tolerance, and thus an overlap of the gate region with the source and drain regions is produced. This overlapping of the gate and the drain and source regions introduces a large parasitic capacitance between the metal gate electrode and the P+ and N+ regions separated by the thin gate oxide layer. This parasitic capacitance reduces the speed of the integrated circuit in operation. It is therefore desirable that a fabrication technique be employed which produces no overlap between the gate and the source and drain regions so that the metal gate electrode over the source and drain regions is separated therefrom by a thick oxide insulation layer rather than the thin gate oxide layer, thus eliminating parasitic capacitance.
A second undesirable feature of the conventional CMOS fabrication results from the misalignment between the N+, P+ and contact opening mask and can severely limit the yield of a large size CMOS circuit. This misalignment dictates that the contact openings must be designed well inside the P+ and N+ diffusion areas in order to compensate the misalignment and mask dimension variation. In order to provide for this variation in contact location, it is necessary that the area of the CMOS structure be greater than desired.
A third undesirable feature of the conventional CMOS process is that the gate oxidation is performed after the N+ and P+ diffusion steps and, since this gate oxidation is performed at a relatively high temperature, the P+ and N+ junction depths cannot be kept as shallow as desired and the resulting surface concentration of impurities is lower than in the case of a process where the gate oxidation is done before the source and drain diffusions.
One known technique for overcoming certain of the above undesirable characteristics of the conventional CMOS technique employs a silicon nitride (Si.sub.3 N.sub.4) mask to define the openings for the P+ and N+ source and drain diffusions, the silicon nitride mask also defining the gate area. After the source and drain diffusion steps, the silicon nitride layer is removed from all areas except the gate regions and a thick silicon oxide layer is grown on all such areas, leaving the silicon nitride over the self-aligned gate areas. After the thick oxide has been grown, the silicon nitride defining the gate regions is selectively etched away and replaced by a thin silicon oxide gate layer. Thereafter the contact openings are made in the thick oxide in the source and drain regions and a metallization step forms the source and drain contacts and the metal gate electrodes. In this self-aligning gate technique there is no overlap of the thin gate oxide and the source and drain regions so that there is no parasitic capacitance of the type described above. However, due to the misalignment of the P+ and N+ diffusion masks, the contact openings through the thick oxide layer and into the P+ and N+ source and drain regions must be designed well within the boundaries of the source and drain regions and the resulting area size for the large scale CMOS structure is undesirably great.